Non-volatile memories may include a single poly Electrically Erasable Programmable Read Only Memory (EEPROM), a stack gate (Electron Tunnel Oxide (ETOX)), a dual poly EEPROM, and a split gate. The single poly EEPROM includes a single polycrystalline silicon layer functioning as a gate, and the stack gate includes two polycrystalline silicon layers vertically stacked one above another. The dual poly EEPROM and the split gate correspond to an intermediate between the single poly EEPROM and the stack gate. The stack gate has the smallest cell size and relatively complicated circuits. Such a stack gate may be suitable for high density and high performance, but may not be suitable for low density. EEPROMs are mainly used for low density. For example, the single poly EEPROM may be manufactured by adding approximately two mask processes during a logic process. However, the single poly EEPROM has a cell size approximately 200 times that of the stack gate, and thus, is not suitable for high density. The dual poly EEPROM and the split gate, which correspond to an intermediate between the single poly EEPROM and the stack gate, have a disadvantage of complicated manufacturing processes.
FIG. 1A illustrates a program method of a single poly EEPROM using channel hot electron injection.
As illustrated in FIG. 1A, if program voltage +Vp is applied to N-well 1A, a predetermined voltage is induced in floating gate 2a. The predetermined voltage induced in floating gate 2a causes inversion of a channel region of an N-channel Metal Oxide Semiconductor (NMOS) device. Here, the voltage induced in floating gate 2a is determined by a coupling ratio. Then, if predetermined voltage VDS is applied to drain region 3 of the NMOS device, current flows from drain region 3 to source region 4. In this case, as channel hot electrons generated near a drain junction are injected into floating gate 2b, a threshold voltage of the NMOS device is increased.
FIG. 1B illustrates an erase method of a single poly EEPROM using Fowler Nordheim (F/N) tunneling.
As illustrated in FIG. 1B, N-well 1 is grounded, and erase voltage +VE is applied to drain region 3 and source region 4 of the NMOS device. With grounded N-well 1, a potential close to a ground level is included in floating gate 2a. Also, with erase voltage +VE applied to drain region 3 and source region 4 of the NMOS device, an electric field is strengthened from drain region 3 and source region 4 of the NMOS device toward floating gate 2b. As electrons in floating gate 2b are moved into drain region 3 and source region 4 under the influence of the electric field, the threshold voltage of the NMOS device is reduced.
FIG. 1C illustrates a reading method of a single poly EEPROM.
As illustrated in FIG. 1C, reading voltage +VR is applied to the N-well 1 and in turn, a predetermined voltage is induced in floating gate 2a by applied reading voltage +VR. A positive drain voltage for a reading operation is applied to drain region 4 of the NMOS device, and source region 4 is grounded. If the NMOS device has a considerably high threshold voltage indicative of a program state in which electrons are injected in floating gate 2b, the NMOS device cannot be turned on even by the predetermined voltage induced in floating gate 2a, and thus, no current flow occurs. On the other hand, if the NMOS device has a considerably low threshold voltage indicative of an erase state in which no electrons are present in floating gate 2b, the NMOS device can be turned on by the predetermined voltage induced in floating gate 2a, and thus, current flow occurs.
Considering endurance characteristics of the above-described single poly EEPROM, electron traps are created in the channel region and the drain/source regions of the NMOS device during program/erase operations. The greater the number of the program/erase operations, i.e., the greater the number of cycles, the greater the number of the electron traps, resulting in a considerable increase in program/erase threshold voltages, more particularly, in an erase threshold voltage.
FIG. 1D is a view illustrating endurance characteristics of the related art.
As illustrated in FIG. 1D, the erase threshold voltage has substantially no variation below 10 cycles, but gradually increases above 10 cycles. Meaning, assuming that a reading voltage is 2.0V, a threshold voltage may exceed 2.0V under the condition of approximately 5,000 to 10,000 cycles. This may cause an operational failure because of a difficulty in making a distinction between a program state and an erase state.